[ { "key": "W5UZTT59", "version": 1, "library": { "type": "group", "id": 4574, "name": "Computer Architecture", "links": { "alternate": { "href": "https://www.zotero.org/groups/computer_architecture", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/4574/items/W5UZTT59", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/computer_architecture/items/W5UZTT59", "type": "text/html" } }, "meta": { "createdByUser": { "id": 44582, "username": "ftabba", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ftabba", "type": "text/html" } } }, "creatorSummary": "Lee et al.", "parsedDate": "2009", "numChildren": 0 }, "data": { "key": "W5UZTT59", "version": 1, "itemType": "journalArticle", "title": "Architecting phase change memory as a scalable DRAM alternative", "creators": [ { "creatorType": "author", "firstName": "Benjamin C.", "lastName": "Lee" }, { "creatorType": "author", "firstName": "Engin", "lastName": "Ipek" }, { "creatorType": "author", "firstName": "Onur", "lastName": "Mutlu" }, { "creatorType": "author", "firstName": "Doug", "lastName": "Burger" } ], "abstractNote": "Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.", "publicationTitle": "SIGARCH Comput. Archit. News", "publisher": "", "place": "", "date": "2009", "volume": "37", "issue": "3", "section": "", "partNumber": "", "partTitle": "", "pages": "2-13", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1145/1555815.1555758", "citationKey": "", "url": "http://portal.acm.org/citation.cfm?id=1555815.1555758", "accessDate": "2009-09-08T03:57:21Z", "PMID": "", "PMCID": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "ACM", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "dram alternative", "type": 1 }, { "tag": "endurance", "type": 1 }, { "tag": "energy", "type": 1 }, { "tag": "pcm", "type": 1 }, { "tag": "performance", "type": 1 }, { "tag": "phase change memory", "type": 1 }, { "tag": "power", "type": 1 }, { "tag": "scalability", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2009-09-10T22:32:34Z", "dateModified": "2009-09-10T22:32:34Z" } }, { "key": "ZRXPP7CS", "version": 1, "library": { "type": "group", "id": 4574, "name": "Computer Architecture", "links": { "alternate": { "href": "https://www.zotero.org/groups/computer_architecture", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/4574/items/ZRXPP7CS", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/computer_architecture/items/ZRXPP7CS", "type": "text/html" } }, "meta": { "createdByUser": { "id": 44582, "username": "ftabba", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ftabba", "type": "text/html" } } }, "creatorSummary": "Herlihy and Moss", "parsedDate": "1993", "numChildren": 0 }, "data": { "key": "ZRXPP7CS", "version": 1, "itemType": "journalArticle", "title": "Transactional memory: architectural support for lock-free data structures", "creators": [ { "creatorType": "author", "firstName": "Maurice", "lastName": "Herlihy" }, { "creatorType": "author", "firstName": "J. Eliot B.", "lastName": "Moss" } ], "abstractNote": "A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be prevented from operating on that object. In highly concurrent systems, lock-free data structures avoid common problems associated with conventional locking techniques, including priority inversion, convoying, and difficulty of avoiding deadlock. This paper introduces transactional memory, a new multiprocessor architecture intended to make lock-free synchronization as efficient (and easy to use) as conventional techniques based on mutual exclusion. Transactional memory allows programmers to define customized read-modify-write operations that apply to multiple, independently-chosen words of memory. It is implemented by straightforward extensions to any multiprocessor cache-coherence protocol. Simulation results show that transactional memory matches or outperforms the best known locking techniques for simple benchmarks, even in the absence of priority inversion, convoying, and deadlock.", "publicationTitle": "SIGARCH Comput. Archit. News", "publisher": "", "place": "", "date": "1993", "volume": "21", "issue": "2", "section": "", "partNumber": "", "partTitle": "", "pages": "289-300", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1145/173682.165164", "citationKey": "", "url": "http://portal.acm.org/citation.cfm?id=165164", "accessDate": "2009-09-08T04:12:36Z", "PMID": "", "PMCID": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "Transactional memory", "language": "", "libraryCatalog": "ACM", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [], "relations": {}, "dateAdded": "2009-09-08T04:12:57Z", "dateModified": "2009-09-08T04:12:57Z" } }, { "key": "MENI8WMM", "version": 1, "library": { "type": "group", "id": 4574, "name": "Computer Architecture", "links": { "alternate": { "href": "https://www.zotero.org/groups/computer_architecture", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/4574/items/MENI8WMM", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/computer_architecture/items/MENI8WMM", "type": "text/html" } }, "meta": { "createdByUser": { "id": 44582, "username": "ftabba", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ftabba", "type": "text/html" } } }, "creatorSummary": "Kuskin et al.", "parsedDate": "1994", "numChildren": 0 }, "data": { "key": "MENI8WMM", "version": 1, "itemType": "conferencePaper", "title": "The Stanford FLASH multiprocessor", "creators": [ { "creatorType": "author", "firstName": "J.", "lastName": "Kuskin" }, { "creatorType": "author", "firstName": "D.", "lastName": "Ofelt" }, { "creatorType": "author", "firstName": "M.", "lastName": "Heinrich" }, { "creatorType": "author", "firstName": "J.", "lastName": "Heinlein" }, { "creatorType": "author", "firstName": "R.", "lastName": "Simoni" }, { "creatorType": "author", "firstName": "K.", "lastName": "Gharachorloo" }, { "creatorType": "author", "firstName": "J.", "lastName": "Chapin" }, { "creatorType": "author", "firstName": "D.", "lastName": "Nakahira" }, { "creatorType": "author", "firstName": "J.", "lastName": "Baxter" }, { "creatorType": "author", "firstName": "M.", "lastName": "Horowitz" }, { "creatorType": "author", "firstName": "A.", "lastName": "Gupta" }, { "creatorType": "author", "firstName": "M.", "lastName": "Rosenblum" }, { "creatorType": "author", "firstName": "J.", "lastName": "Hennessy" } ], "abstractNote": "The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine's global memory, a port to the interconnection network, an I/O interface, and a custom node controller called MAGIC. The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The use of the protocol processor makes FLASH very flexible --- it can support a variety of different communication mechanisms --- and simplifies the design and implementation.This paper presents the architecture of FLASH and MAGIC, and discusses the base cache-coherence and message-passing protocols. Latency and occupancy numbers, which are derived from our system-level simulator and our Verilog code, are given for several common protocol operations. The paper also describes our software strategy and FLASH's current status.", "proceedingsTitle": "Proceedings of the 21st annual international symposium on Computer architecture", "conferenceName": "", "publisher": "IEEE Computer Society Press", "place": "Chicago, Illinois, United States", "date": "1994", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "302-313", "series": "", "seriesNumber": "", "DOI": "10.1145/191995.192056", "ISBN": "0-8186-5510-0", "citationKey": "", "url": "http://portal.acm.org/citation.cfm?id=191995.192056", "accessDate": "2009-09-08T03:59:00Z", "ISSN": "", "archive": "ACM", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [], "relations": {}, "dateAdded": "2009-09-08T03:59:14Z", "dateModified": "2009-09-08T03:59:14Z" } }, { "key": "N3NCAVWW", "version": 1, "library": { "type": "group", "id": 4574, "name": "Computer Architecture", "links": { "alternate": { "href": "https://www.zotero.org/groups/computer_architecture", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/4574/items/N3NCAVWW", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/computer_architecture/items/N3NCAVWW", "type": "text/html" } }, "meta": { "createdByUser": { "id": 44582, "username": "ftabba", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ftabba", "type": "text/html" } } }, "creatorSummary": "Tabba et al.", "parsedDate": "2009", "numChildren": 0 }, "data": { "key": "N3NCAVWW", "version": 1, "itemType": "conferencePaper", "title": "NZTM: nonblocking zero-indirection transactional memory", "creators": [ { "creatorType": "author", "firstName": "Fuad", "lastName": "Tabba" }, { "creatorType": "author", "firstName": "Mark", "lastName": "Moir" }, { "creatorType": "author", "firstName": "James R.", "lastName": "Goodman" }, { "creatorType": "author", "firstName": "Andrew W.", "lastName": "Hay" }, { "creatorType": "author", "firstName": "Cong", "lastName": "Wang" } ], "abstractNote": "This paper introduces NZTM, a nonblocking, zero-indirection, object-based, hybrid transactional memory system. NZTM comprises a nonblocking software transactional memory (STM) system that can exploit best-effort hardware transactional memory (HTM) if available to improve performance.", "proceedingsTitle": "Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures", "conferenceName": "", "publisher": "ACM", "place": "Calgary, AB, Canada", "date": "2009", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "204-213", "series": "", "seriesNumber": "", "DOI": "10.1145/1583991.1584048", "ISBN": "978-1-60558-606-9", "citationKey": "", "url": "http://portal.acm.org/citation.cfm?id=1583991.1584048&coll=Portal&dl=GUIDE&CFID=51838884&CFTOKEN=53267280", "accessDate": "2009-09-08T03:53:41Z", "ISSN": "", "archive": "ACM", "archiveLocation": "", "shortTitle": "NZTM", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "hardware support", "type": 1 }, { "tag": "nonblocking synchronization", "type": 1 }, { "tag": "transactional memory", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2009-09-08T03:53:59Z", "dateModified": "2009-09-08T03:53:59Z" } }, { "key": "PG2VPC6B", "version": 1, "library": { "type": "group", "id": 4574, "name": "Computer Architecture", "links": { "alternate": { "href": "https://www.zotero.org/groups/computer_architecture", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/4574/items/PG2VPC6B", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/computer_architecture/items/PG2VPC6B", "type": "text/html" } }, "meta": { "createdByUser": { "id": 44582, "username": "ftabba", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ftabba", "type": "text/html" } } }, "creatorSummary": "Tabba et al.", "parsedDate": "2007-01-01", "numChildren": 0 }, "data": { "key": "PG2VPC6B", "version": 1, "itemType": "journalArticle", "title": "NZTM: Nonblocking Zero-Indirection Transactional Memory", "creators": [ { "creatorType": "author", "firstName": "F", "lastName": "Tabba" }, { "creatorType": "author", "firstName": "C", "lastName": "Wang" }, { "creatorType": "author", "firstName": "JR", "lastName": "Goodman" }, { "creatorType": "author", "firstName": "M", "lastName": "Moir" } ], "abstractNote": "", "publicationTitle": "the 2nd ACM SIGPLAN Workshop on Transactional Computing", "publisher": "", "place": "", "date": "January 01, 2007", "volume": "", "issue": "", "section": "", "partNumber": "", "partTitle": "", "pages": "", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "the 2nd ACM SIGPLAN Workshop on Transactional Computing", "DOI": "", "citationKey": "", "url": "http://research.sun.com/people/moir/pubs/TRANSACT2007-NZTM.pdf", "accessDate": "", "PMID": "", "PMCID": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "4329846382097289070", "tags": [], "collections": [], "relations": {}, "dateAdded": "2009-09-08T03:46:46Z", "dateModified": "2009-09-08T03:46:46Z" } } ]