[ { "key": "7BAZGGBG", "version": 25, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/7BAZGGBG", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/7BAZGGBG", "type": "text/html" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } }, "creatorSummary": "Biswas", "parsedDate": "2014", "numChildren": 1 }, "data": { "key": "7BAZGGBG", "version": 25, "itemType": "thesis", "title": "Energy-efficient SRAM design in 28nm FDSOI Technology", "creators": [ { "creatorType": "author", "firstName": "Avishek", "lastName": "Biswas" } ], "abstractNote": "As CMOS scaling continues to sub-32nm regime, the effects of device variations become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate at lower supply voltages (Vdd). This is due to the significant degradation of functional margins as the supply voltage is scaled down. However, Vdd scaling is crucial in reducing the energy consumption of SRAMs, which is a significant portion of the overall energy consumption in modern micro-processors. Energy savings in SRAM is particularly important for batteryoperated applications, which run from a very constrained power-budget. This thesis focuses on energy-efficient 6T SRAM design in a 28nm FDSOI technology. Significant savings in energy/access of the SRAM is achieved using two techniques: Vdd scaling and data prediction. A 200mV improvement in the minimum SRAM operating voltage (Vdd,min) is achieved by using dynamic forward body-biasing (FBB) on the NMOS devices of the bit-cell. The overhead of dynamic FBB is reduced by implementing it row-wise. Layout modifications are proposed to share the body terminals (n-wells) horizontally, along a row. Further savings in energy/access is achieved by incoporating data-prediction in the 6T read path, which reduces bitline switching. The proposed techniques are implemented for a 128Kb 6T SRAM, designed in a 28nm FDSOI technology. This thesis also presents a reconfigurable fully-integrated switched-capacitor based step-up DC-DC converter, which can be used to generate the body-bias voltage for a SRAM. 3 reconfigurable conversion ratios of 5/2, 2/1 and 3/2 are implemented in the converter. It provides a wide range of output voltage, 1.2V-2.4V, from a fixed input of 1V. The converter achieves a peak efficiency of 88%, using only on-chip MOS and MOM capacitors, for a high density implementation.", "thesisType": "Thesis", "university": "Massachusetts Institute of Technology", "place": "", "date": "2014", "series": "", "seriesNumber": "", "numPages": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "http://dspace.mit.edu/handle/1721.1/91095", "accessDate": "2014-10-31T16:59:01Z", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "eng", "libraryCatalog": "dspace.mit.edu", "callNumber": "", "rights": "http://dspace.mit.edu/handle/1721.1/7582", "extra": "Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.", "tags": [ { "tag": "Electrical Engineering and Computer Science.", "type": 1 } ], "collections": [ "BFNGDXCT" ], "relations": {}, "dateAdded": "2014-10-31T16:59:01Z", "dateModified": "2014-10-31T16:59:01Z" } }, { "key": "ZJZT8SM2", "version": 25, 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"text/html" } } } }, "data": { "key": "Q9952R8V", "version": 23, "parentItem": "T3338PAJ", "itemType": "attachment", "linkMode": "linked_url", "title": "IEEE Xplore Full Text PDF", "accessDate": "2014-10-29T09:56:46Z", "url": "http://ieeexplore.ieee.org/ielx7/6708497/6716503/06716525.pdf?tp=&arnumber=6716525&isnumber=6716503", "note": "", "contentType": "application/pdf", "charset": "", "tags": [], "relations": {}, "dateAdded": "2014-10-29T09:56:46Z", "dateModified": "2014-10-29T09:56:46Z" } }, { "key": "T3338PAJ", "version": 23, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/T3338PAJ", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/T3338PAJ", "type": "text/html" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } }, "creatorSummary": "Feki et al.", "parsedDate": "2013-10", "numChildren": 2 }, "data": { "key": "T3338PAJ", "version": 23, "itemType": "conferencePaper", "title": "280mV sense amplifier designed in 28nm UTBB FD-SOI technology using back-biasing control", "creators": [ { "creatorType": "author", "firstName": "A.", "lastName": "Feki" }, { "creatorType": "author", "firstName": "D.", "lastName": "Turgis" }, { "creatorType": "author", "firstName": "J.C.", "lastName": "Lafont" }, { "creatorType": "author", "firstName": "B.", "lastName": "Allard" } ], "abstractNote": "Sub-threshold operation of circuits becomes more and more attractive due to the ultra-low power consumption. Static Random Access Memory (SRAM) faces an important limitation in read access time that prevents high frequency operation and the possible applications. The read access time under ultra-low voltage (ULV) operation is mainly dictated by the read current of the SRAM bit cell and the bit line effective capacitance. The full swing sensing is a practical approach to circumvent the poor performances of sense amplifiers (SA) under ULV operation. This paper details first the optimization of a differential voltage-sense amplifier under ULV for SRAMs with differential bit lines. Second an unbalanced voltage-sense amplifier is presented for single-ended reading under ULV. Both circuits exploit the benefit of 28nm FDSOI and back biasing technique to improve SAs' performances, namely the delay. Both ultra-wide voltage-range SAs achieve satisfying operation down to 280mV power supply. Simulation results are presented regarding a 1K×32 L1 cache test chip to be fabricated in 28FDSOI technology.", "proceedingsTitle": "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)", "conferenceName": "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)", "publisher": "", "place": "", "date": "October 2013", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "1-2", "series": "", "seriesNumber": "", "DOI": "10.1109/S3S.2013.6716525", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Capacitance", "type": 1 }, { "tag": "Delay", "type": 1 }, { "tag": "Delays", "type": 1 }, { "tag": "Differential sensing", "type": 1 }, { "tag": "FDSOI", "type": 1 }, { "tag": "Offset", "type": 1 }, { "tag": "Optimization", "type": 1 }, { "tag": "Random access memory", "type": 1 }, { "tag": "SRAM", "type": 1 }, { "tag": "SRAM bit cell", "type": 1 }, { "tag": "SRAM chips", "type": 1 }, { "tag": "Sensors", "type": 1 }, { "tag": "Simulation", "type": 1 }, { "tag": "Sub-threshold Design", "type": 1 }, { "tag": "Threshold voltage", "type": 1 }, { "tag": "Time-frequency analysis", "type": 1 }, { "tag": "ULV Bit-cell", "type": 1 }, { "tag": "UTBB FD-SOI technology", "type": 1 }, { "tag": "Unbalanced sense amplifier", "type": 1 }, { "tag": "back-biasing control", "type": 1 }, { "tag": "bit line effective capacitance", "type": 1 }, { "tag": "circuit optimisation", "type": 1 }, { "tag": "differential amplifiers", "type": 1 }, { "tag": "differential voltage-sense amplifier", "type": 1 }, { "tag": "full swing sensing", "type": 1 }, { "tag": "low-power electronics", "type": 1 }, { "tag": "read access time", "type": 1 }, { "tag": "silicon-on-insulator", "type": 1 }, { "tag": "single-ended reading", "type": 1 }, { "tag": "size 28 nm", "type": 1 }, { "tag": "static random access memory", "type": 1 }, { "tag": "subthreshold operation", "type": 1 }, { "tag": "ultralow power consumption", "type": 1 }, { "tag": "ultralow voltage operation", "type": 1 }, { "tag": "unbalanced voltage-sense amplifier", "type": 1 }, { "tag": "voltage 280 mV", "type": 1 } ], "collections": [ "BFNGDXCT" ], "relations": {}, "dateAdded": "2014-10-29T09:56:46Z", "dateModified": "2014-10-29T09:56:46Z" } }, { "key": "CWK2VSPJ", "version": 24, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/CWK2VSPJ", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/CWK2VSPJ", "type": "text/html" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } }, "creatorSummary": "D.) and Sachdev", "parsedDate": "2008-06-01", "numChildren": 1 }, "data": { "key": "CWK2VSPJ", "version": 24, "itemType": "book", "title": "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test", "creators": [ { "creatorType": "author", "firstName": "Andrei Pavlov (Ph", "lastName": "D.)" }, { "creatorType": "author", "firstName": "Manoj", "lastName": "Sachdev" } ], "abstractNote": "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.", "series": "", "seriesNumber": "", "volume": "", "numberOfVolumes": "", "edition": "", "date": "2008-06-01", "publisher": "Springer Science & Business Media", "place": "", "originalDate": "", "originalPublisher": "", "originalPlace": "", "format": "", "numPages": "203", "ISBN": "9781402083631", "DOI": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies", "language": "en", "libraryCatalog": "Google Books", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Computers / Hardware / General", "type": 1 }, { "tag": "Technology & Engineering / Electronics / Semiconductors", "type": 1 }, { "tag": "Technology & Engineering / Nanotechnology & MEMS", "type": 1 } ], "collections": [ "BFNGDXCT", "CXXGFQK8" ], "relations": {}, "dateAdded": "2014-10-29T08:22:54Z", "dateModified": "2014-10-29T08:22:54Z" } }, { "key": "CTFBF7DK", "version": 21, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/CTFBF7DK", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/CTFBF7DK", "type": "text/html" }, "up": { "href": "https://api.zotero.org/groups/294169/items/CWK2VSPJ", "type": "application/json" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } } }, "data": { "key": "CTFBF7DK", "version": 21, "parentItem": "CWK2VSPJ", "itemType": "attachment", "linkMode": "linked_url", "title": "Google Books Link", "accessDate": "2014-10-29T08:22:54Z", "url": "http://books.google.no/books?id=OXigu7wLa34C", "note": "", "contentType": "text/html", "charset": "", "tags": [], "relations": {}, "dateAdded": "2014-10-29T08:22:54Z", "dateModified": "2014-10-29T08:22:54Z" } }, { "key": "7QK2B93S", "version": 19, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/7QK2B93S", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/7QK2B93S", "type": "text/html" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } }, "creatorSummary": "de Streel and Bol", "parsedDate": "2013-09", "numChildren": 2 }, "data": { "key": "7QK2B93S", "version": 19, "itemType": "conferencePaper", "title": "Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology", "creators": [ { "creatorType": "author", "firstName": "G.", "lastName": "de Streel" }, { "creatorType": "author", "firstName": "D.", "lastName": "Bol" } ], "abstractNote": "Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP.", "proceedingsTitle": "2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)", "conferenceName": "2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)", "publisher": "", "place": "", "date": "Sept 2013", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "255-260", "series": "", "seriesNumber": "", "DOI": "10.1109/ISLPED.2013.6629305", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "28nm", "type": 1 }, { "tag": "CMOS FDSOI", "type": 1 }, { "tag": "CMOS integrated circuits", "type": 1 }, { "tag": "Delays", "type": 1 }, { "tag": "Logic gates", "type": 1 }, { "tag": "MEP", "type": 1 }, { "tag": "MOS devices", "type": 1 }, { "tag": "NMOS", "type": 1 }, { "tag": "Noise", "type": 1 }, { "tag": "PMOS", "type": 1 }, { "tag": "Robustness", "type": 1 }, { "tag": "Systematics", "type": 1 }, { "tag": "UTBB FDSOI technology", "type": 1 }, { "tag": "asymmetric back biasing", "type": 1 }, { "tag": "back gate biasing", "type": 1 }, { "tag": "design space", "type": 1 }, { "tag": "die yield", "type": 1 }, { "tag": "forward back biasing scheme", "type": 1 }, { "tag": "integrated circuit design", "type": 1 }, { "tag": "leakage currents", "type": 1 }, { "tag": "low-power electronics", "type": 1 }, { "tag": "minimum energy point", "type": 1 }, { "tag": "silicon-on-insulator", "type": 1 }, { "tag": "size 28 nm", "type": 1 }, { "tag": "subthreshold logic", "type": 1 }, { "tag": "ultra-low power", "type": 1 }, { "tag": "ultra-low voltage logic", "type": 1 }, { "tag": "ultra-low-voltage", "type": 1 } ], "collections": [ "PKSAPIDK" ], "relations": {}, "dateAdded": "2014-10-27T08:34:15Z", "dateModified": "2014-10-27T08:34:15Z" } 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"meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } }, "creatorSummary": "Bernard et al.", "parsedDate": "2013-10", "numChildren": 2 }, "data": { "key": "JTJEPR8I", "version": 18, "itemType": "conferencePaper", "title": "Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology", "creators": [ { "creatorType": "author", "firstName": "S.", "lastName": "Bernard" }, { "creatorType": "author", "firstName": "A.", "lastName": "Valentian" }, { "creatorType": "author", "firstName": "M.", "lastName": "Belleville" }, { "creatorType": "author", "firstName": "D.", "lastName": "Bol" }, { "creatorType": "author", "firstName": "J.-D.", "lastName": "Legat" } ], "abstractNote": "So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.", "proceedingsTitle": "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)", "conferenceName": "2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)", "publisher": "", "place": "", "date": "October 2013", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "1-2", "series": "", "seriesNumber": "", "DOI": "10.1109/S3S.2013.6716555", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Clocks", "type": 1 }, { "tag": "Delays", "type": 1 }, { "tag": "Latches", "type": 1 }, { "tag": "Pulse generation", "type": 1 }, { "tag": "Robustness", "type": 1 }, { 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"2013-09", "numChildren": 2 }, "data": { "key": "NHA7HSHD", "version": 16, "itemType": "conferencePaper", "title": "Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control", "creators": [ { "creatorType": "author", "firstName": "V.", "lastName": "Asthana" }, { "creatorType": "author", "firstName": "M.", "lastName": "Kar" }, { "creatorType": "author", "firstName": "J.", "lastName": "Jimenez" }, { "creatorType": "author", "firstName": "J.-P.", "lastName": "Noel" }, { "creatorType": "author", "firstName": "S.", "lastName": "Haendler" }, { "creatorType": "author", "firstName": "P.", "lastName": "Galy" } ], "abstractNote": "SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. 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"text/html" } } }, "creatorSummary": "Texas Instruments", "parsedDate": "2011-08-17", "numChildren": 0 }, "data": { "key": "SC5TAABM", "version": 9, "itemType": "videoRecording", "title": "Advancements in Low Power with Professor Chandrakasan (MIT)", "creators": [ { "creatorType": "contributor", "name": "Texas Instruments" } ], "abstractNote": "University and Industry Work Together to Drive Low Power Advances -- Anantha Chandrakasan, Professor of Electrical Engineering and Director of the Microsystems Technology Labs at MIT, joins TI Fellow, Ray Simar, and host John Dixon for a discussion on advancements in low power technology and the roles both industry and academia must play.", "videoRecordingFormat": "", "seriesTitle": "", "volume": "", "numberOfVolumes": "", "studio": "", "place": "", "date": "2011-08-17", "runningTime": "719 seconds", "ISBN": "", "DOI": "", "citationKey": "", "url": "http://www.youtube.com/watch?v=lyg1aEyHt74&feature=youtube_gdata_player", "accessDate": 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"itemType": "conferencePaper", "title": "6T SRAM design for wide voltage range in 28nm FDSOI", "creators": [ { "creatorType": "author", "firstName": "O.", "lastName": "Thomas" }, { "creatorType": "author", "firstName": "B.", "lastName": "Zimmer" }, { "creatorType": "author", "firstName": "B.", "lastName": "Pelloux-Prayer" }, { "creatorType": "author", "firstName": "N.", "lastName": "Planes" }, { "creatorType": "author", "firstName": "K.-C.", "lastName": "Akyel" }, { "creatorType": "author", "firstName": "L.", "lastName": "Ciampolini" }, { "creatorType": "author", "firstName": "P.", "lastName": "Flatresse" }, { "creatorType": "author", "firstName": "B.", "lastName": "Nikolic" } ], "abstractNote": "Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.", "proceedingsTitle": "SOI Conference (SOI), 2012 IEEE International", "conferenceName": "SOI Conference (SOI), 2012 IEEE International", "publisher": "", "place": "", "date": "October 2012", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "1-2", "series": "", "seriesNumber": "", "DOI": "10.1109/SOI.2012.6404393", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "6T SRAM design", "type": 1 }, { "tag": "Bit error rate", "type": 1 }, { "tag": "Clocks", "type": 1 }, { "tag": "HD 6T SPW array", "type": 1 }, { "tag": "High definition video", "type": 1 }, { "tag": "MOSFETs", "type": 1 }, { "tag": "Random access memory", "type": 1 }, { "tag": "SPW bit cell design", "type": 1 }, { "tag": "SRAM chips", "type": 1 }, { "tag": "UTBB FDSOI technology", "type": 1 }, { "tag": "active mode", "type": 1 }, { "tag": "back-bias voltage range", "type": 1 }, { "tag": "dynamic failure metrics", "type": 1 }, { "tag": "failure analysis", "type": 1 }, { "tag": "high-density 6-transistor SRAM", "type": 1 }, { "tag": "high-performance portable applications", "type": 1 }, { "tag": "integrated circuit design", "type": 1 }, { "tag": "integrated circuit reliability", "type": 1 }, { "tag": "leakage current", "type": 1 }, { "tag": "leakage currents", "type": 1 }, { "tag": "silicon-on-insulator", "type": 1 }, { "tag": "single p-well bit cell design", "type": 1 }, { "tag": "size 28 nm", "type": 1 }, { "tag": "sleep mode", "type": 1 }, { "tag": "transient simulations", "type": 1 }, { "tag": "ultra-thin body and buried oxide FDSOI technology", "type": 1 }, { "tag": "voltage 0.65 V", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2014-10-06T12:39:24Z", "dateModified": "2014-10-06T12:39:24Z" } }, { "key": "73AV8I3Q", "version": 6, "library": { "type": "group", "id": 294169, "name": "SubthresholdDesign", "links": { "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/294169/items/73AV8I3Q", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/subthresholddesign/items/73AV8I3Q", "type": "text/html" }, "up": { "href": "https://api.zotero.org/groups/294169/items/C37UTEJW", "type": "application/json" } }, "meta": { "createdByUser": { "id": 2111097, "username": "even.laate", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/even.laate", "type": "text/html" } } } }, "data": { "key": "73AV8I3Q", "version": 6, "parentItem": "C37UTEJW", "itemType": "attachment", "linkMode": "linked_url", "title": "IEEE Xplore Abstract Record", "accessDate": "2014-10-06T12:39:24Z", "url": "http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6404393", "note": "", "contentType": "text/html", "charset": "", "tags": [], "relations": {}, "dateAdded": "2014-10-06T12:39:24Z", "dateModified": "2014-10-06T12:39:24Z" } } ]