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Our design incorporates heterogeneous cores representing different points in the power/performance design space; during an application's execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements. Our evaluation of this architecture shows significant energy benefits. For an objective function that optimizes for energy efficiency with a tight performance threshold, for 14 SPEC benchmarks, our results indicate a 39% average energy reduction while only sacrificing 3% in performance. An objective function that optimizes for energy-delay with looser performance bounds achieves, on average, nearly a factor of three improvements in energy-delay product while sacrificing only 22% in performance. Energy savings are substantially more than chip-wide voltage/frequency scaling.", "proceedingsTitle": "36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. Proceedings", "conferenceName": "36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. Proceedings", "publisher": "", "place": "", "date": "2003", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "81-92", "series": "", "seriesNumber": "", "DOI": "10.1109/MICRO.2003.1253185", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "Single-ISA heterogeneous multi-core architectures", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Application software", "type": 1 }, { "tag": "Clocks", "type": 1 }, { "tag": "Computer science", "type": 1 }, { "tag": "Energy consumption", "type": 1 }, { "tag": "Frequency", "type": 1 }, { "tag": "Milling machines", "type": 1 }, { "tag": "Power dissipation", "type": 1 }, { "tag": "Power engineering and energy", "type": 1 }, { "tag": "SPEC benchmarks", "type": 1 }, { "tag": "application execution", "type": 1 }, { "tag": "chip-wide frequency scaling", "type": 1 }, { "tag": "chip-wide voltage scaling", "type": 1 }, { "tag": "computer architecture", "type": 1 }, { "tag": "energy delay", "type": 1 }, { "tag": "energy efficiency", "type": 1 }, { "tag": "energy savings", "type": 1 }, { "tag": "heterogeneous cores", "type": 1 }, { "tag": "low-power electronics", "type": 1 }, { "tag": "microprocessor chips", "type": 1 }, { "tag": "performance design space", "type": 1 }, { "tag": "power design space", "type": 1 }, { "tag": "processor power reduction", "type": 1 }, { "tag": "single-ISA heterogeneous multicore architectures", "type": 1 }, { "tag": "system software", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "FP9CE9NS", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/FP9CE9NS", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/FP9CE9NS", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Paul et al.", "parsedDate": "2006", "numChildren": 1 }, "data": { "key": "FP9CE9NS", "version": 2, "itemType": "journalArticle", "title": "Scenario-oriented design for single-chip heterogeneous multiprocessors", "creators": [ { "creatorType": "author", "firstName": "J.M.", "lastName": "Paul" }, { "creatorType": "author", "firstName": "D.E.", "lastName": "Thomas" }, { "creatorType": "author", "firstName": "A.", "lastName": "Bobrek" } ], "abstractNote": "Single-chip heterogeneous multiprocessors (SCHMs) are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation community, general-purpose designs traditionally targeted by the computer architecture community, nor pure embedded designs traditionally targeted by the real-time community. An entirely new design philosophy will be needed for this hybrid class of computing. The programming of the device will be drawn from a narrower set of applications with execution that persists in the system over a longer period of time than for general-purpose programming. However, the devices will still be programmable, not only at the level of the individual processing element, but across multiple processing elements and even the entire chip. The design of other programmable single chip computers has enjoyed an era where the design tradeoffs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks. Motivated by this, we describe new benchmark-based design strategies for SCHMs which we refer to as scenario-oriented design. We include an example and results", "publicationTitle": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", "publisher": "", "place": "", "date": "2006", "volume": "14", "issue": "8", "section": "", "partNumber": "", "partTitle": "", "pages": "868-880", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1109/TVLSI.2006.878474", "citationKey": "", "url": "", "accessDate": "", "PMID": "", "PMCID": "", "ISSN": "1063-8210", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Application software", "type": 1 }, { "tag": "Benchmarking", "type": 1 }, { "tag": "Computational modeling", "type": 1 }, { "tag": "Computer simulation", "type": 1 }, { "tag": "Design automation", "type": 1 }, { "tag": "Embedded computing", "type": 1 }, { "tag": "Handheld computers", "type": 1 }, { "tag": "Pervasive computing", "type": 1 }, { "tag": "Portable computers", "type": 1 }, { "tag": "Real time systems", "type": 1 }, { "tag": "SPEC benchmarks", "type": 1 }, { "tag": "SimpleScalar", "type": 1 }, { "tag": "computer architecture", "type": 1 }, { "tag": "design methodology", "type": 1 }, { "tag": "general-purpose programming", "type": 1 }, { "tag": "heterogeneous multiprocessor", "type": 1 }, { "tag": "individual processing element", "type": 1 }, { "tag": "logic design", "type": 1 }, { "tag": "modeling", "type": 1 }, { "tag": "multiple processing elements", "type": 1 }, { "tag": "multiprocessing systems", "type": 1 }, { "tag": "programmable single chip computers", "type": 1 }, { "tag": "scenario-oriented design", "type": 1 }, { "tag": "single-chip heterogeneous multiprocessors", "type": 1 }, { "tag": "system-on-chip", "type": 1 }, { "tag": "system-on-chip (SOC)", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "7R4HRGI9", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/7R4HRGI9", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/7R4HRGI9", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Watkins and Albonesi", "parsedDate": "2010", "numChildren": 1 }, "data": { "key": "7R4HRGI9", "version": 2, "itemType": "conferencePaper", "title": "ReMAP: A Reconfigurable Heterogeneous Multicore Architecture", "creators": [ { "creatorType": "author", "firstName": "M.A.", "lastName": "Watkins" }, { "creatorType": "author", "firstName": "D.H.", "lastName": "Albonesi" } ], "abstractNote": "This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common reconfigurable fabric that can be configured for individual thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained point-to-point communication for pipeline parallelization and fine-grained barrier synchronization. The combination of communication and configurable computation within ReMAP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. ReMAP demonstrates significantly higher performance and energy efficiency compared to hard-wired communication-only mechanisms, and over what can ideally be achieved by allocating the fabric area to additional or more powerful cores.", "proceedingsTitle": "2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)", "conferenceName": "2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)", "publisher": "", "place": "", "date": "2010", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "497-508", "series": "", "seriesNumber": "", "DOI": "10.1109/MICRO.2010.15", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "ReMAP", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "ReMAP", "type": 1 }, { "tag": "fine-grained barrier synchronization", "type": 1 }, { "tag": "fine-grained point-to-point communication", "type": 1 }, { "tag": "hard-wired communication-only mechanisms", "type": 1 }, { "tag": "large-scale chip multiprocessors", "type": 1 }, { "tag": "microprocessor chips", "type": 1 }, { "tag": "multiprocessing systems", "type": 1 }, { "tag": "parallel architectures", "type": 1 }, { "tag": "pipeline parallelization", "type": 1 }, { "tag": "pipeline processing", "type": 1 }, { "tag": "reconfigurable architectures", "type": 1 }, { "tag": "reconfigurable fabric", "type": 1 }, { "tag": "reconfigurable heterogeneous multicore architecture", "type": 1 }, { "tag": "synchronisation", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "SGC3F868", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/SGC3F868", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/SGC3F868", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Kumar et al.", "parsedDate": "2003", "numChildren": 1 }, "data": { "key": "SGC3F868", "version": 2, "itemType": "journalArticle", "title": "Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures", "creators": [ { "creatorType": "author", "firstName": "R.", "lastName": "Kumar" }, { "creatorType": "author", "firstName": "K.", "lastName": "Farkas" }, { "creatorType": "author", "firstName": "N.P.", "lastName": "Jouppi" }, { "creatorType": "author", "firstName": "P.", "lastName": "Ranganathan" }, { "creatorType": "author", "firstName": "D.M.", "lastName": "Tullsen" } ], "abstractNote": "This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application’s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.", "publicationTitle": "Computer Architecture Letters", "publisher": "", "place": "", "date": "2003", "volume": "2", "issue": "1", "section": "", "partNumber": "", "partTitle": "", "pages": "2-2", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1109/L-CA.2003.6", "citationKey": "", "url": "", "accessDate": "", "PMID": "", "PMCID": "", "ISSN": "1556-6056", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Application software", "type": 1 }, { "tag": "Computer science", "type": 1 }, { "tag": "Costs", "type": 1 }, { "tag": "Energy consumption", "type": 1 }, { "tag": "Fans", "type": 1 }, { "tag": "Packaging", "type": 1 }, { "tag": "Power dissipation", "type": 1 }, { "tag": "Power engineering and energy", "type": 1 }, { "tag": "chip multiprocessor", "type": 1 }, { "tag": "computer architecture", "type": 1 }, { "tag": "low-power architecture", "type": 1 }, { "tag": "system software", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "HS968UB4", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/HS968UB4", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/HS968UB4", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Linderman et al.", "parsedDate": "2008-03", "numChildren": 0 }, "data": { "key": "HS968UB4", "version": 2, "itemType": "journalArticle", "title": "Merge: a programming model for heterogeneous multi-core systems", "creators": [ { "creatorType": "author", "firstName": "Michael D.", "lastName": "Linderman" }, { "creatorType": "author", "firstName": "Jamison D.", "lastName": "Collins" }, { "creatorType": "author", "firstName": "Hong", "lastName": "Wang" }, { "creatorType": "author", "firstName": "Teresa H.", "lastName": "Meng" } ], "abstractNote": "In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to parallel programming on heterogeneous platforms with a rigorous, library-based methodology that can automatically distribute computation across heterogeneous cores to achieve increased energy and performance efficiency. The Merge framework provides (1) a predicate dispatch-based library system for managing and invoking function variants for multiple architectures; (2) a high-level, library-oriented parallel language based on map-reduce; and (3) a compiler and runtime which implement the map-reduce language pattern by dynamically selecting the best available function implementations for a given input and machine configuration. Using a generic sequencer architecture interface for heterogeneous accelerators, the Merge framework can integrate function variants for specialized accelerators, offering the potential for to-the-metal performance for a wide range of heterogeneous architectures, all transparent to the user. The Merge framework has been prototyped on a heterogeneous platform consisting of an Intel Core 2 Duo CPU and an 8-core 32-thread Intel Graphics and Media Accelerator X3000, and a homogeneous 32-way Unisys SMP system with Intel Xeon processors. We implemented a set of benchmarks using the Merge framework and enhanced the library with X3000 specific implementations, achieving speedups of 3.6x -- 8.5x using the X3000 and 5.2x -- 22x using the 32-way system relative to the straight C reference implementation on a single IA32 core.", "publicationTitle": "SIGPLAN Not.", "publisher": "", "place": "", "date": "March 2008", "volume": "43", "issue": "3", "section": "", "partNumber": "", "partTitle": "", "pages": "287–296", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1145/1353536.1346318", "citationKey": "", "url": "http://doi.acm.org/10.1145/1353536.1346318", "accessDate": "2013-05-07T04:26:30Z", "PMID": "", "PMCID": "", "ISSN": "0362-1340", "archive": "", "archiveLocation": "", "shortTitle": "Merge", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "GPGPU", "type": 1 }, { "tag": "heterogeneous multi-core", "type": 1 }, { "tag": "predicate dispatch", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "3ZPEW3RP", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/3ZPEW3RP", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/3ZPEW3RP", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Auerbach et al.", "parsedDate": "2010-10", "numChildren": 0 }, "data": { "key": "3ZPEW3RP", "version": 2, "itemType": "journalArticle", "title": "Lime: a Java-compatible and synthesizable language for heterogeneous architectures", "creators": [ { "creatorType": "author", "firstName": "Joshua", "lastName": "Auerbach" }, { "creatorType": "author", "firstName": "David F.", "lastName": "Bacon" }, { "creatorType": "author", "firstName": "Perry", "lastName": "Cheng" }, { "creatorType": "author", "firstName": "Rodric", "lastName": "Rabbah" } ], "abstractNote": "The halt in clock frequency scaling has forced architects and language designers to look elsewhere for continued improvements in performance. We believe that extracting maximum performance will require compilation to highly heterogeneous architectures that include reconfigurable hardware. We present a new language, Lime, which is designed to be executable across a broad range of architectures, from FPGAs to conventional CPUs. We present the language as a whole, focusing on its novel features for limiting side-effects and integration of the streaming paradigm into an object- oriented language. We conclude with some initial results demonstrating applications running either on a CPU or co- executing on a CPU and an FPGA.", "publicationTitle": "SIGPLAN Not.", "publisher": "", "place": "", "date": "October 2010", "volume": "45", "issue": "10", "section": "", "partNumber": "", "partTitle": "", "pages": "89–108", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1145/1932682.1869469", "citationKey": "", "url": "http://doi.acm.org/10.1145/1932682.1869469", "accessDate": "2013-05-07T04:12:32Z", "PMID": "", "PMCID": "", "ISSN": "0362-1340", "archive": "", "archiveLocation": "", "shortTitle": "Lime", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "fpga", "type": 1 }, { "tag": "functional programming", "type": 1 }, { "tag": "high level synthesis", "type": 1 }, { "tag": "object oriented", "type": 1 }, { "tag": "reconfigurable architecture", "type": 1 }, { "tag": "streaming", "type": 1 }, { "tag": "value type", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "65GP3MCQ", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/65GP3MCQ", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/65GP3MCQ", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Chafi et al.", "parsedDate": "2010-10", "numChildren": 0 }, "data": { "key": "65GP3MCQ", "version": 2, "itemType": "journalArticle", "title": "Language virtualization for heterogeneous parallel computing", "creators": [ { "creatorType": "author", "firstName": "Hassan", "lastName": "Chafi" }, { "creatorType": "author", "firstName": "Zach", "lastName": "DeVito" }, { "creatorType": "author", "firstName": "Adriaan", "lastName": "Moors" }, { "creatorType": "author", "firstName": "Tiark", "lastName": "Rompf" }, { "creatorType": "author", "firstName": "Arvind K.", "lastName": "Sujeeth" }, { "creatorType": "author", "firstName": "Pat", "lastName": "Hanrahan" }, { "creatorType": "author", "firstName": "Martin", "lastName": "Odersky" }, { "creatorType": "author", "firstName": "Kunle", "lastName": "Olukotun" } ], "abstractNote": "As heterogeneous parallel systems become dominant, application developers are being forced to turn to an incompatiblemix of low level programming models (e.g. OpenMP, MPI, CUDA, OpenCL). However, these models do little to shield developers from the difficult problems of parallelization, data decomposition and machine-specific details. Most programmersare having a difficult time using these programming models effectively. To provide a programming modelthat addresses the productivity and performance requirements for the average programmer, we explore a domainspecificapproach to heterogeneous parallel programming. We propose language virtualization as a new principle that enables the construction of highly efficient parallel domain specific languages that are embedded in a common host language. We define criteria for language virtualization and present techniques to achieve them.We present two concrete case studies of domain-specific languages that are implemented using our virtualization approach.", "publicationTitle": "SIGPLAN Not.", "publisher": "", "place": "", "date": "October 2010", "volume": "45", "issue": "10", "section": "", "partNumber": "", "partTitle": "", "pages": "835–847", "series": "", "seriesTitle": "", "seriesText": "", "journalAbbreviation": "", "DOI": "10.1145/1932682.1869527", "citationKey": "", "url": "http://doi.acm.org/10.1145/1932682.1869527", "accessDate": "2013-05-07T04:03:55Z", "PMID": "", "PMCID": "", "ISSN": "0362-1340", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "domain specific languages", "type": 1 }, { "tag": "dynamic optimizations", "type": 1 }, { "tag": "parallel programming", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "URXHZZ7R", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/URXHZZ7R", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/URXHZZ7R", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Kumar et al.", "parsedDate": "2005", "numChildren": 1 }, "data": { "key": "URXHZZ7R", "version": 2, "itemType": "conferencePaper", "title": "Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling", "creators": [ { "creatorType": "author", "firstName": "R.", "lastName": "Kumar" }, { "creatorType": "author", "firstName": "V.", "lastName": "Zyuban" }, { "creatorType": "author", "firstName": "D.M.", "lastName": "Tullsen" } ], "abstractNote": "This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multi-core design. Several examples are presented showing the need for careful co-design. For instance, increasing interconnect bandwidth requires area that then constrains the number of cores or cache sizes, and does not necessarily increase performance. Also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. A hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.", "proceedingsTitle": "32nd International Symposium on Computer Architecture, 2005. ISCA '05. Proceedings", "conferenceName": "32nd International Symposium on Computer Architecture, 2005. ISCA '05. Proceedings", "publisher": "", "place": "", "date": "2005", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "408-419", "series": "", "seriesNumber": "", "DOI": "10.1109/ISCA.2005.34", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "Interconnections in multi-core architectures", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "Bandwidth", "type": 1 }, { "tag": "Computer science", "type": 1 }, { "tag": "Delay", "type": 1 }, { "tag": "Design engineering", "type": 1 }, { "tag": "Joining processes", "type": 1 }, { "tag": "Power engineering and energy", "type": 1 }, { "tag": "Power system interconnection", "type": 1 }, { "tag": "Space exploration", "type": 1 }, { "tag": "Space technology", "type": 1 }, { "tag": "cache storage", "type": 1 }, { "tag": "chip multiprocessor", "type": 1 }, { "tag": "computer architecture", "type": 1 }, { "tag": "hierarchical bus structure", "type": 1 }, { "tag": "interconnect architectures", "type": 1 }, { "tag": "interconnect bandwidth", "type": 1 }, { "tag": "interconnections", "type": 1 }, { "tag": "microprocessor chips", "type": 1 }, { "tag": "multicore architectures", "type": 1 }, { "tag": "multicore design", "type": 1 }, { "tag": "multiprocessor interconnection networks", "type": 1 }, { "tag": "on-chip interconnects", "type": 1 }, { "tag": "parallel architectures", "type": 1 }, { "tag": "performance evaluation", "type": 1 }, { "tag": "system buses", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "6XVUP3IC", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/6XVUP3IC", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/6XVUP3IC", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Kollig et al.", "parsedDate": "2009", "numChildren": 1 }, "data": { "key": "6XVUP3IC", "version": 2, "itemType": "conferencePaper", "title": "Heterogeneous multi-core platform for consumer multimedia applications", "creators": [ { "creatorType": "author", "firstName": "P.", "lastName": "Kollig" }, { "creatorType": "author", "firstName": "C.", "lastName": "Osborne" }, { "creatorType": "author", "firstName": "T.", "lastName": "Henriksson" } ], "abstractNote": "This paper presents a multi-core SoC architecture for consumer multimedia applications. The comprehensive functionality of such multimedia systems is described using the example of a hybrid TV application. The successful usage of a heterogeneous multi-core SoC platform is presented and it is shown how specific challenges such as inter-processor communication and real-time performance guarantees in physically centralized memory systems are addressed.", "proceedingsTitle": "Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09.", "conferenceName": "Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09.", "publisher": "", "place": "", "date": "2009", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "1254-1259", "series": "", "seriesNumber": "", "DOI": "10.1109/DATE.2009.5090857", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "IEEE Xplore", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "CMOS technology", "type": 1 }, { "tag": "Computer industry", "type": 1 }, { "tag": "Consumer electronics", "type": 1 }, { "tag": "Decoding", "type": 1 }, { "tag": "Message passing", "type": 1 }, { "tag": "Microcontrollers", "type": 1 }, { "tag": "Multimedia systems", "type": 1 }, { "tag": "Parallel processing", "type": 1 }, { "tag": "SoC architecture", "type": 1 }, { "tag": "TV", "type": 1 }, { "tag": "centralized memory systems", "type": 1 }, { "tag": "component", "type": 1 }, { "tag": "computer architecture", "type": 1 }, { "tag": "consumer multimedia applications", "type": 1 }, { "tag": "heterogeneous multicore platform", "type": 1 }, { "tag": "hybrid TV application", "type": 1 }, { "tag": "interprocessor communication", "type": 1 }, { "tag": "memory architecture", "type": 1 }, { "tag": "multimedia communication", "type": 1 }, { "tag": "multiprocessor", "type": 1 }, { "tag": "physically centralized memory system", "type": 1 }, { "tag": "real-time performance", "type": 1 }, { "tag": "system-on-chip", "type": 1 }, { "tag": "telecommunication networks", "type": 1 }, { "tag": "television applications", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "MN2IMVPZ", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/MN2IMVPZ", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/MN2IMVPZ", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Diamos and Yalamanchili", "parsedDate": "2008", "numChildren": 0 }, "data": { "key": "MN2IMVPZ", "version": 2, "itemType": "conferencePaper", "title": "Harmony: an execution model and runtime for heterogeneous many core systems", "creators": [ { "creatorType": "author", "firstName": "Gregory F.", "lastName": "Diamos" }, { "creatorType": "author", "firstName": "Sudhakar", "lastName": "Yalamanchili" } ], "abstractNote": "The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by matching certain classes of algorithms to specifically tailored architectures. Their ubiquitous adoption, however, has been limited by a lack of programming models and management frameworks designed to reduce the high degree of complexity of software development intrinsic to heterogeneous architectures. This paper proposes Harmony, a runtime supported programming and execution model that provides: (1) semantics for simplifying parallelism management, (2) dynamic scheduling of compute intensive kernels to heterogeneous processor resources, and (3) online monitoring driven performance optimization for heterogeneous many core systems. We are particulably concerned with simplifying development and ensuring binary portability and scalability across system configurations and sizes. Initial results from ongoing development demonstrate the binary compatibility with variable number of cores, as well as dynamic adaptation of schedules to data sets. We present preliminary results of key features for some benchmark applications.", "proceedingsTitle": "Proceedings of the 17th international symposium on High performance distributed computing", "conferenceName": "", "publisher": "ACM", "place": "New York, NY, USA", "date": "2008", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "197–200", "series": "HPDC '08", "seriesNumber": "", "DOI": "10.1145/1383422.1383447", "ISBN": "978-1-59593-997-5", "citationKey": "", "url": "http://doi.acm.org/10.1145/1383422.1383447", "accessDate": "2013-05-07T04:46:49Z", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "Harmony", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "GPGPU", "type": 1 }, { "tag": "dependency graph", "type": 1 }, { "tag": "harmony", "type": 1 }, { "tag": "heterogeneous", "type": 1 }, { "tag": "many core", "type": 1 }, { "tag": "optimization", "type": 1 }, { "tag": "performance monitoring", "type": 1 }, { "tag": "runtime", "type": 1 }, { "tag": "scheduling", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "FDFA28V2", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/FDFA28V2", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/FDFA28V2", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Cong and Yuan", "parsedDate": "2012", "numChildren": 0 }, "data": { "key": "FDFA28V2", "version": 2, "itemType": "conferencePaper", "title": "Energy-efficient scheduling on heterogeneous multi-core architectures", "creators": [ { "creatorType": "author", "firstName": "Jason", "lastName": "Cong" }, { "creatorType": "author", "firstName": "Bo", "lastName": "Yuan" } ], "abstractNote": "The use of heterogeneous multi-core architectures has increased because of their potential energy efficiency compared to the homogeneous multi-core architectures. The shift from homogeneous multi-core to heterogeneous multi-core architectures creates many challenges for scheduling applications on the heterogeneous multi-core system. This paper studies the energy-efficient scheduling on Intel's QuickIA heterogeneous prototype platform [6]. A regression model is developed to estimate the energy consumption on the real heterogeneous multi-core platform. Our scheduling approach maps the program to the most appropriate core, based on program phases, through a combination of static analysis and runtime scheduling. We demonstrate the energy efficiency of our phase-based scheduling method by comparing it against the statical mapping approach proposed in [5] and the periodic sampling based approach proposed in [11], The experimental results show that our scheduling scheme can achieve an average 10.20% reduction in the energy delay product compared to [5] and an average 19.81% reduction in energy delay product compared to [11].", "proceedingsTitle": "Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design", "conferenceName": "", "publisher": "ACM", "place": "New York, NY, USA", "date": "2012", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "345–350", "series": "ISLPED '12", "seriesNumber": "", "DOI": "10.1145/2333660.2333737", "ISBN": "978-1-4503-1249-3", "citationKey": "", "url": "http://doi.acm.org/10.1145/2333660.2333737", "accessDate": "2013-05-07T05:08:01Z", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "energy efficiency", "type": 1 }, { "tag": "heterogeneous multi-core", "type": 1 }, { "tag": "scheduling", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } }, { "key": "AH9VK8IB", "version": 2, "library": { "type": "group", "id": 167858, "name": "Heterogeneous Architectures", "links": { "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/167858/items/AH9VK8IB", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/heterogeneous_architectures/items/AH9VK8IB", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1401175, "username": "ldsolano17", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/ldsolano17", "type": "text/html" } } }, "creatorSummary": "Kumar et al.", "parsedDate": "2006", "numChildren": 0 }, "data": { "key": "AH9VK8IB", "version": 2, "itemType": "conferencePaper", "title": "Core architecture optimization for heterogeneous chip multiprocessors", "creators": [ { "creatorType": "author", "firstName": "Rakesh", "lastName": "Kumar" }, { "creatorType": "author", "firstName": "Dean M.", "lastName": "Tullsen" }, { "creatorType": "author", "firstName": "Norman P.", "lastName": "Jouppi" } ], "abstractNote": "Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores.This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets.The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics - no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.", "proceedingsTitle": "Proceedings of the 15th international conference on Parallel architectures and compilation techniques", "conferenceName": "", "publisher": "ACM", "place": "New York, NY, USA", "date": "2006", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "23–32", "series": "PACT '06", "seriesNumber": "", "DOI": "10.1145/1152154.1152162", "ISBN": "1-59593-264-X", "citationKey": "", "url": "http://doi.acm.org/10.1145/1152154.1152162", "accessDate": "2013-05-07T04:22:07Z", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "ACM Digital Library", "callNumber": "", "rights": "", "extra": "", "tags": [ { "tag": "computer architecture", "type": 1 }, { "tag": "heterogeneous chip multiprocessors", "type": 1 }, { "tag": "multi-core architectures", "type": 1 } ], "collections": [], "relations": {}, "dateAdded": "2013-05-15T05:03:27Z", "dateModified": "2013-05-15T05:03:27Z" } } ]