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"itemType": "encyclopediaArticle", "title": "MSI protocol", "creators": [], "abstractNote": "In computing, the MSI protocol - a basic cache-coherence protocol - operates in multiprocessor systems. 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It is the most common protocol which supports write-back cache. Its use in personal computers became widespread with the introduction of Intel's Pentium processor to \"support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor\".[2]", "encyclopediaTitle": "Wikipedia, the free encyclopedia", "series": "", "seriesNumber": "", "volume": "", "numberOfVolumes": "", "edition": "", "date": "2013-05-02T14:22:35Z", "publisher": "", "place": "", "pages": "", "ISBN": "", "DOI": "", "citationKey": "", "url": "http://en.wikipedia.org/w/index.php?title=MESI_protocol&oldid=549729600", "accessDate": "2013-05-06T01:42:35Z", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "en", "libraryCatalog": "Wikipedia", "callNumber": "", "rights": "Creative Commons Attribution-ShareAlike License", "extra": "Page Version ID: 549729600", "tags": [], "collections": [], "relations": {}, "dateAdded": "2013-05-11T05:07:31Z", "dateModified": "2013-05-11T05:07:31Z" } }, { "key": "WWTBF4NC", "version": 2, "library": { "type": "group", "id": 166954, "name": "arqui_cache coherency protocols", "links": { "alternate": { "href": "https://www.zotero.org/groups/arqui_cache_coherency_protocols", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166954/items/WWTBF4NC", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arqui_cache_coherency_protocols/items/WWTBF4NC", "type": "text/html" } }, "meta": { "createdByUser": { "id": 319498, "username": "chango2251991", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/chango2251991", "type": "text/html" } } }, "creatorSummary": "Eggers and Katz", "parsedDate": "1989-04", "numChildren": 0 }, "data": { "key": "WWTBF4NC", "version": 2, "itemType": "journalArticle", "title": "Evaluating the performance of four snooping cache coherency protocols", "creators": [ { "creatorType": "author", "firstName": "S. J.", "lastName": "Eggers" }, { "creatorType": "author", "firstName": "R. H.", "lastName": "Katz" } ], "abstractNote": "Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. Read-broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem.\nOur results indicate that the benefits of the extensions are limited. Read-broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. The net effect can be an increase in total execution cycles. Competitive snooping benefits only those programs with high per-processor locality of reference to shared data. For programs characterized by inter-processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.", "publicationTitle": "SIGARCH Comput. Archit. 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