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Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness", "accessDate": "", "url": "", "note": "", "contentType": "application/pdf", "charset": "", "filename": "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness", "md5": "4a824a8f95b5f9be628a3f2a03640e35", "mtime": 1368336099942, "tags": [], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "4HI5CE5T", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/4HI5CE5T", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/4HI5CE5T", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Jung et al.", "numChildren": 1 }, "data": { "key": "4HI5CE5T", "version": 3, "itemType": "conferencePaper", "title": "Tradeoff between Data-, Instruction-, and Thread-Level Parallelism in Stream Processors", "creators": [ { "creatorType": "author", "firstName": "Ho", "lastName": "Jung" }, { "creatorType": "author", "firstName": "Erez", "lastName": "Mattan" }, { "creatorType": "author", "firstName": "Dally", "lastName": "William" } ], "abstractNote": "This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and processorperformance models for a multi-threaded Stream Processor and\nevaluate the tradeoffs, in both functionality and hardware costs,\nof mechanisms that exploit the different types of parallelism.\nWe show that the hardware overhead of supporting coarsegrained independent threads of control is 15 −86% depending\non machine parameters. We also demonstrate that the performance gains provided are of a smaller magnitude for a set of\nnumerical applications. We argue that for stream applications\nwith scalable parallel algorithms the performance is not very\nsensitive to the control structures used within a large range of\narea-efficient architectural choices. We evaluate the specific effects on performance of scaling along the different parallelism\ndimensions and explain the limitations of the ILP, DLP, and\nTLP hardware mechanisms.", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "5BWGZKXV", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/5BWGZKXV", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/5BWGZKXV", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Jeffrey et al.", "numChildren": 1 }, "data": { "key": "5BWGZKXV", "version": 3, "itemType": "conferencePaper", "title": "In Search of Speculative Thread-Level Parallelism", "creators": [ { "creatorType": "author", "firstName": "Oplinger", "lastName": "Jeffrey" }, { "creatorType": "author", "firstName": "Heine", "lastName": "David" }, { "creatorType": "author", "firstName": "Lam", "lastName": "Monica" } ], "abstractNote": "This paper focuses on the problem of how to find and effectively\nexploit speculative thread-level parallelism. Our studies show\nthat speculating only on loops does not yield sufficient\nparallelism. We propose the use of speculative procedure\nexecution as a means to increase the available parallelism. An\nadditional technique, data value prediction, has the potential to\ngreatly improve the performance of speculative execution. In\nparticular, return value prediction improves the success of\nprocedural speculation, and stride value prediction improves the\nsuccess of loop speculation.", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "XN7CZHGN", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/XN7CZHGN", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/XN7CZHGN", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Krisztián et al.", "numChildren": 1 }, "data": { "key": "XN7CZHGN", "version": 3, "itemType": "conferencePaper", "title": "Thread-level Parallelism and Interactive Performance of Desktop Applications", "creators": [ { "creatorType": "author", "firstName": "Flautner", "lastName": "Krisztián" }, { "creatorType": "author", "firstName": "Uhlig", "lastName": "Rich" }, { "creatorType": "author", "firstName": "Reinhardt", "lastName": "Steve" }, { "creatorType": "author", "firstName": "Mudge", "lastName": "Trevor" } ], "abstractNote": "Multiprocessing is already prevalent in servers where\nmultiple clients present an obvious source of thread-level\nparallelism. However, the case for multiprocessing is less\nclear for desktop applications. Nevertheless, architects are\ndesigning processors that count on the availability of\nthread-level parallelism. Unlike server workloads, the primary\nrequirement of interactive applications is to respond\nto user events under human perception bounds rather than\nto maximize end-to-end throughput. In this paper we report\non the thread-level parallelism and interactive response\ntime of a variety of desktop applications. By tracking the\ncommunication between tasks, we can focus our measurements\non the portions of the benchmark’s execution that\nhave the greatest impact on the user. We find that running\nour benchmarks on a dual-processor machine improves\nresponse time of mouse-click events by as much as 36%, and\n22% on average—out of a maximum possible 50%. The\nbenefits of multiprocessing are even more apparent when\nbackground tasks are considered. In our experiments, running\na simple MP3 playback program in the background\nincreases response time by 14% on a uniprocessor while it\nonly increases the response time on a dual processor by 4%.\nWhen response times are fast enough for further improvements\nto be imperceptible, the increased idle time after\ninteractive episodes could", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "54C98MVV", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/54C98MVV", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/54C98MVV", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "T. N. et al.", "numChildren": 1 }, "data": { "key": "54C98MVV", "version": 3, "itemType": "conferencePaper", "title": "Multiplex: Unifying Conventional and Speculative Thread-Level Parallelism on a Chip Multiprocessor", "creators": [ { "creatorType": "author", "firstName": "Vijaykumar", "lastName": "T. N." }, { "creatorType": "author", "firstName": "Liang", "lastName": "Chong" }, { "creatorType": "author", "firstName": "Wook", "lastName": "Seon" }, { "creatorType": "author", "firstName": "Park", "lastName": "Il" }, { "creatorType": "author", "firstName": "Eigenmann", "lastName": "Rudolf" }, { "creatorType": "author", "firstName": "Falsafi", "lastName": "Babak" } ], "abstractNote": "Recent proposals for Chip Multiprocessors (CMPs) advocate speculative,\nor implicit, threading in which the hardware employs prediction\nto peel off instruction sequences (i.e., implicit threads)\nfrom the sequential execution stream and speculatively executes\nthem in parallel on multiple processor cores. These proposals augment\na conventional multiprocessor, which employs explicit\nthreading, with the ability to handle implicit threads. Current proposals\nfocus on only implicitly-threaded code sections. This paper\nidentifies, for the first time, the issues in combining explicit and\nimplicit threading. We present the Multiplex architecture to combine\nthe two threading models. Multiplex exploits the similarities\nbetween implicit and explicit threading, and provides a unified\nsupport for the two threading models without additional hardware.\nMultiplex groups a subset of protocol states in an implicitlythreaded\nCMP to provide a write-invalidate protocol for explicit\nthreads.\nUsing a fully-integrated compiler infrastructure for automatic generation\nof Multiplex code, this paper presents a detailed performance\nanalysis for entire benchmarks, instead of just implicitlythreaded\nsections, as done in previous papers.We show that neither\nthreading models alone performs consistently better than the other\nacross the benchmarks. A CMP with four dual-issue CPUs\nachieves a speedup of 1.48 and 2.17 over one dual-issue CPU,\nusing implicit-only and explicit-only threading, respectively. Multiplex\nmatches or outperforms the better of the two threading models\nfor every benchmark, and a four-CPU Multiplex achieves a\nspeedup of 2.63. Our detailed analysis indicates that the dominant\noverheads in an implicitly-threaded CMP are speculation state\noverflow due to limited L1 cache capacity, and load imbalance and\ndata dependences in fine-grain threads.", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "XKD526KK", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/XKD526KK", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/XKD526KK", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Nikolas and Marcelo", "numChildren": 1 }, "data": { "key": "XKD526KK", "version": 3, "itemType": "conferencePaper", "title": "Complementing User-Level Coarse-Grain Parallelism with Implicit Speculative Parallelism", "creators": [ { "creatorType": "author", "firstName": "Ioannou", "lastName": "Nikolas" }, { "creatorType": "author", "firstName": "Cintra", "lastName": "Marcelo" } ], "abstractNote": "Multi-core and many-core systems are the norm in contemporary processor technology and are expected to remain so\nfor the foreseeable future. Programs using parallel programming primitives like PThreads or OpenMP often exploit\ncoarse-grain parallelism, because it offers a good trade-off\nbetween programming effort versus performance gain. Some\nparallel applications show limited or no scaling beyond a\nnumber of cores. Given the abundant number of cores expected in future many-cores, several cores would remain idle\nin such cases while execution performance stagnates. This\npaper proposes using cores that do not contribute to performance improvement for running implicit fine-grain speculative threads. In particular, we present a many-core architecture and protocol that allow applications with coarsegrain explicit parallelism to further exploit implicit speculative parallelism within each thread. Implicit speculative\nparallelism frees the programmer from the additional effort\nto explicitly partition the work into finer and properly synchronized tasks. Our results show that, for a many-core\ncomprising of 128 cores supporting implicit speculative parallelism in clusters of 2 or 4 cores, performance improves on\ntop of the highest scalability point by 41% on average for the\n4-core cluster and by 27% on average for the 2-core cluster.\nThese performance improvements come with an energy consumption that is close to – and sometimes better than – the\nbaseline. This approach often leads to better performance\nand energy efficiency compared to existing alternatives such\nas Core Fusion and Frequency Boosting. We also investigate\nthe tradeoffs between explicit and implicit threads as input\ndataset sizes vary. Finally, we present a dynamic mechanism\nto choose the number of explicit and implicit threads, which\nperforms within 6% of the static oracle selection of threads.", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "IF4NQ4DI", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/IF4NQ4DI", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/IF4NQ4DI", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "J.Gregory et al.", "numChildren": 1 }, "data": { "key": "IF4NQ4DI", "version": 3, "itemType": "conferencePaper", "title": "Architectural Support for Thread-Level Data Speculation", "creators": [ { "creatorType": "author", "firstName": "Steffan", "lastName": "J.Gregory" }, { "creatorType": "author", "firstName": "Colohan", "lastName": "Christofer" }, { "creatorType": "author", "firstName": "Mowry", "lastName": "Todd" } ], "abstractNote": "", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "R87PAUT2", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/R87PAUT2", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/R87PAUT2", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Theo et al.", "numChildren": 1 }, "data": { "key": "R87PAUT2", "version": 3, "itemType": "conferencePaper", "title": "A Survey of Processors with Explicit Multithreading", "creators": [ { "creatorType": "author", "firstName": "Ungerer", "lastName": "Theo" }, { "creatorType": "author", "firstName": "Robic", "lastName": "Borut" }, { "creatorType": "author", "firstName": "Silc", "lastName": "Jurij" } ], "abstractNote": "Hardware multithreading is becoming a generally applied technique in the next\ngeneration of microprocessors. Several multithreaded processors are announced by\nindustry or already into production in the areas of high-performance microprocessors,\nmedia, and network processors.\nA multithreaded processor is able to pursue two or more threads of control in parallel\nwithin the processor pipeline. The contexts of two or more threads of control are often\nstored in separate on-chip register sets. Unused instruction slots, which arise from\nlatencies during the pipelined execution of single-threaded programs by a contemporary\nmicroprocessor, are filled by instructions of other threads within a multithreaded\nprocessor. The execution units are multiplexed between the thread contexts that are\nloaded in the register sets.\nUnderutilization of a superscalar processor due to missing instruction-level\nparallelism can be overcome by simultaneous multithreading, where a processor can\nissue multiple instructions from multiple threads each cycle. Simultaneous\nmultithreaded processors combine the multithreading technique with a wide-issue\nsuperscalar processor to utilize a larger part of the issue bandwidth by issuing\ninstructions from different threads simultaneously.\nExplicit multithreaded processors are multithreaded processors that apply processes\nor operating system threads in their hardware thread slots. These processors optimize\nthe throughput of multiprogramming workloads rather than single-thread\nperformance. We distinguish these processors from implicit multithreaded processors", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "34CP44SU", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/34CP44SU", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/34CP44SU", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Karsten and Nitesh", "numChildren": 1 }, "data": { "key": "34CP44SU", "version": 3, "itemType": "conferencePaper", "title": "Scalable Learning with Thread-Level Parallelism", "creators": [ { "creatorType": "author", "firstName": "Steinhaeuser", "lastName": "Karsten" }, { "creatorType": "author", "firstName": "Chawla", "lastName": "Nitesh" } ], "abstractNote": "", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "RKW7KWZ9", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/RKW7KWZ9", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/RKW7KWZ9", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Henry et al.", "numChildren": 1 }, "data": { "key": "RKW7KWZ9", "version": 3, "itemType": "conferencePaper", "title": "An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors", "creators": [ { "creatorType": "author", "firstName": "Levy", "lastName": "Henry" }, { "creatorType": "author", "firstName": "Swanson", "lastName": "Steven" }, { "creatorType": "author", "firstName": "McDowell", "lastName": "Luke" }, { "creatorType": "author", "firstName": "Swift", "lastName": "Michael" }, { "creatorType": "author", "firstName": "Eggers", "lastName": "Susan" } ], "abstractNote": "Modern superscalar processors rely heavily on speculative execution for performance. For example,\nour measurements show that on a 6-issue superscalar, 93% of committed instructions for\nSPECINT95 are speculative. Without speculation, processor resources on such machines would\nbe largely idle. In contrast to superscalars, simultaneous multithreaded (SMT) processors achieve\nhigh resource utilization by issuing instructions from multiple threads every cycle. An SMT processor\nthus has two means of hiding latency: speculation and multithreaded execution. However, these\ntwo techniques may conflict; on an SMT processor, wrong-path speculative instructions from one\nthread may compete with and displace useful instructions from another thread. For this reason, it\nis important to understand the trade-offs between these two latency-hiding techniques, and to ask\nwhether multithreaded processors should speculate differently than conventional superscalars.\nThis paper evaluates the behavior of instruction speculation on SMT processors using both multiprogrammed\n(SPECINT and SPECFP) and multithreaded (the ApacheWeb server) workloads.We\nmeasure and analyze the impact of speculation and demonstrate how speculation on an 8-context\nSMTdiffers from superscalar speculation.We also examine the effect of speculation-aware fetch and\nbranch prediction policies in the processor. Our results quantify the extent to which (1) speculation\nis critical to performance on a multithreaded processor because it ensures an ample supply of parallelism\nto feed the functional units, and (2) SMT actually enhances the effectiveness of speculative\nexecution, compared to a superscalar processor by reducing the impact of branch misprediction.\nFinally, we quantify the impact of both hardware configuration and workload characteristics on\nspeculation’s usefulness", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } }, { "key": "HBGX97JJ", "version": 3, "library": { "type": "group", "id": 166026, "name": "Arquitectura de Computadores CE", "links": { "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce", "type": "text/html" } } }, "links": { "self": { "href": "https://api.zotero.org/groups/166026/items/HBGX97JJ", "type": "application/json" }, "alternate": { "href": "https://www.zotero.org/groups/arquitectura_de_computadores_ce/items/HBGX97JJ", "type": "text/html" } }, "meta": { "createdByUser": { "id": 1392858, "username": "jandro1491", "name": "", "links": { "alternate": { "href": "https://www.zotero.org/jandro1491", "type": "text/html" } } }, "creatorSummary": "Sunpyo and Hyesoon", "numChildren": 1 }, "data": { "key": "HBGX97JJ", "version": 3, "itemType": "conferencePaper", "title": "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness", "creators": [ { "creatorType": "author", "firstName": "Hong", "lastName": "Sunpyo" }, { "creatorType": "author", "firstName": "Kim", "lastName": "Hyesoon" } ], "abstractNote": "GPU architectures are increasingly important in the multi-core era\ndue to their high number of parallel processors. Programming thousands\nof massively parallel threads is a big challenge for software\nengineers, but understanding the performance bottlenecks of those\nparallel programs on GPU architectures to improve application performance\nis even more difficult. Current approaches rely on programmers\nto tune their applications by exploiting the design space\nexhaustively without fully understanding the performance characteristics\nof their applications.\nTo provide insights into the performance bottlenecks of parallel\napplications on GPU architectures, we propose a simple analytical\nmodel that estimates the execution time of massively parallel programs.\nThe key component of our model is estimating the number\nof parallel memory requests (we call this the memory warp parallelism)\nby considering the number of running threads and memory\nbandwidth. Based on the degree of memory warp parallelism, the\nmodel estimates the cost of memory requests, thereby estimating\nthe overall execution time of a program. Comparisons between\nthe outcome of the model and the actual execution time in several\nGPUs show that the geometric mean of absolute error of our model\non micro-benchmarks is 5.4% and on GPU computing applications\nis 13.3%. All the applications are written in the CUDA programming\nlanguage.", "proceedingsTitle": "", "conferenceName": "", "publisher": "", "place": "", "date": "", "eventPlace": "", "volume": "", "issue": "", "numberOfVolumes": "", "pages": "", "series": "", "seriesNumber": "", "DOI": "", "ISBN": "", "citationKey": "", "url": "", "accessDate": "", "ISSN": "", "archive": "", "archiveLocation": "", "shortTitle": "", "language": "", "libraryCatalog": "", "callNumber": "", "rights": "", "extra": "", "tags": [], "collections": [ "KMM85SW5" ], "relations": {}, "dateAdded": "2013-05-12T06:13:52Z", "dateModified": "2013-05-12T06:13:52Z" } } ]